A Tri-Band Two-Stage LNA with Simultaneous Linearity and Gain Enhancement for WiFi
Original price was: ₹12,000.00.₹8,000.00Current price is: ₹8,000.00.
Source : Tanner EDA
Base paper abstract:
This brief presents a tri-band, two-stage compact low-noise amplifier (LNA) that simultaneously enhances linearity, gain, and noise performance for WiFi applications. The second stage adopts a dual-path architecture, consisting of a main amplifier and an additional amplifier. The additional amplifier, biased in the subthreshold region, suppresses third-order nonlinearity and enhances gain without increasing power consumption. The first-stage LNA reduces the noise contribution from the second stage, improving overall noise performance. To further minimize power consumption, an inverter-based topology is employed. Fabricated in a 90-nm CMOS process, the proposed LNA achieves an S11 below −5 dB at 2.4, 5, and 6 GHz, covering key WiFi bands. At 6-GHz band, it delivers 13.5-dB gain, 3.2-dBm third-order input intercept point (IIP3), and 3.1-dB noise figure (NF). At 5-GHz band, it achieves 15-dB gain, 0.7-dBm IIP3, and 2.76-dB NF. At 2.4-GHz band, it provides 20.66-dB gain, −7-dBm IIP3, and 2.7-dB NF. The circuit consumes only 3 mW of dc power. Measurements at 6 GHz show that the dual-path technique in the second stage improves IIP3 by 8.6 dB, increases gain by 1.5 dB, and reduces NF by 0.6 dB, all without additional power or area overhead.
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Proposed abstract:
Low-noise amplifiers (LNAs) are one of the most important building blocks in wireless communication systems, Internet of Things (IoT) devices, WiFi transceivers, sensor networks, and portable RF applications because they amplify weak received signals while maintaining low distortion and low power consumption. Although conventional LNA architectures provide high gain and good RF performance, they often suffer from high power consumption, larger silicon area, and increased implementation complexity, especially when advanced RF techniques are incorporated. Several existing works have focused on improving gain, linearity, and noise performance; however, many of these designs are implemented using older CMOS technologies and primarily evaluate RF characteristics without investigating the effect of different input excitation methods on circuit performance. To address these limitations, this work presents a power-efficient two-stage low-noise amplifier implemented using 45 nm CMOS technology and verified in the Tanner EDA design environment. The proposed design evaluates the amplifier under both sinusoidal and pulse-width modulation (PWM) input excitations to investigate their influence on power consumption, propagation delay, and voltage gain. The novelty of this work lies in performing a comparative analysis of two different input excitation techniques on the same LNA architecture, demonstrating that PWM excitation significantly reduces power consumption while maintaining comparable voltage gain and stable operating characteristics. Simulation results show that the proposed LNA occupies an area of 1.093 µm² with six MOSFETs and operates from a 0.6 V supply. The design achieves an estimated voltage gain of approximately 15.56 dB, an average power consumption of 944.82 µW under sinusoidal excitation and 422.74 µW under PWM excitation, representing nearly 55% power reduction, with propagation delays of 1.6045 µs and 1.6195 µs, respectively. These results confirm that the proposed implementation provides an energy-efficient and compact solution suitable for future low-power RF integrated circuit applications.
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Design and Performance Analysis of a 45nm CMOS Two Stage Low Noise Amplifier under Sinusoidal and PWM Excitation.
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Original price was: ₹12,000.00.₹8,000.00Current price is: ₹8,000.00.