Name: A Pipelined Fused Multiply-Add Architecture for Configurable FP16 Multi-Operand Operations
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A Pipelined Fused Multiply-Add Architecture for Configurable FP16 Multi-Operand Operations

Source : Verilog HDL

Base Paper Abstract:

Multiple precision modes are needed for a floating-point processing element (PE) because they provide flexibility in handling different types of numerical data with varying levels of precision and performance metrics. Performing high-precision floating-point operations has the benefits of producing highly precise and accurate results while allowing for a greater range of numerical representation. Conversely, low-precision operations offer faster computation speeds and lower power consumption. In this paper, we propose a configurable multi-precision processing element (PE) which supports Half Precision, Single Precision, Double Precision, BrainFloat-16 (BF-16) and TensorFloat-32 (TF-32). The design is realized using GPDK 45 nm technology and operated at 281.9 MHz clock frequency. The design was also implemented on Xilinx ZCU104 FPGA evaluation board. Compared with previous state-of-the-art (SOTA) multiprecision PEs, the proposed design supports two more floating point data formats namely BF-16 and TF-32. It achieves the best energy performance with 2368.91 GFLOPS/W and offers 63% improvement in operating

List of the following materials will be included with the Downloaded Backup:

1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)

2. Existing and Proposed Project Comparison with output video

3. Basic Documentation (20 to 30 Pages):

3.1 Proposed Title

3.2 Proposed Abstract

3.3 Advantages & Disadvantages

3.4 Improvement of this Project

3.5 Existing System with Notes

3.6 Proposed System with Notes

3.7 Literature Survey

3.8 Software Related Notes

3.9 VLSI and HDL Language / Tanner Notes

3.10 References & Reference Paper for More Pages

4. Online Support ( Any Desk / Zoom / Google Meet)

Improvement of this project:

The main objective of this project is to design, implement, and verify a pipelined fused multiply-add (FMA) processing element for FP16 (half-precision) floating-point operations. The architecture aims to efficiently compute the operation r = A × B + C × D for two pairs of FP16 numbers, using a modular pipeline structure.

This project also aims to:

Develop and connect individual hardware modules for each major block in the data path, including input pre-processing, exponent comparison, multipliers, alignment shifter, adder, normalization, and output selection.
Enable detailed observation of the outputs at every stage of the pipeline, to support step-by-step debugging and analysis using binary test inputs.
Ensure correct and reliable operation of each stage through simulation and test bench verification.

The ultimate goal is to create a flexible, high-speed, and easily verifiable FMA unit that can serve as a core building block in signal processing, AI accelerators, or embedded VLSI applications where FP16 computations are critical.

Software Implementation:

Modelsim
Vivado

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