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scaleTRIM: Scalable TRuncation-Based Integer Approximate Multiplier With Linearization and Compensation
Original price was: ₹20,000.00.₹16,000.00Current price is: ₹16,000.00.
Source : Verilog HDL
Base paper abstract:
In this paper, we propose a scalable approximate multiplier design, scaleTRIM, that approximates the multiplication operation using fitted linear functions, also referred to as linearization. We show that multiplication operations can be completely replaced by low-cost addition and bit-wise shift operations by exploiting linearization. Moreover, our proposed design utilizes a lookup table (LUT)-based compensation unit as a novel error-reduction method. In essence, input operands are truncated to a reduced bit-width representation (i.e., h bits) based on their leading-one positions. Then, a curve-fitting method is employed to map the product term to a linear function. Additionally, a piecewise constant error-correction term is used to reduce the approximation error. To compute the piecewise constant, we divide the function space into M segments and average the errors within each segment. In particular, our multiplier supports various degrees of truncation and error compensation to offer a range of accuracy-efficiency trade-offs. The proposed multiplier improves the Mean Relative Error Distance (MRED) by about 15.2% while satisfying the efficiency constraint and improves the Power Delay Product (PDP) by about 22.8% while satisfying the accuracy and efficiency constraints compared to different state-of-the-art approximate multipliers. From a usability perspective, our evaluation of the proposed design for image classification using Deep Neural Networks (DNNs) demonstrates that scaleTRIM offers a better accuracy-efficiency trade-off than state-of-the-art approximate multiplier designs.
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2. Existing and Proposed Project Comparison with output video
3. Basic Documentation (20 to 30 Pages):
3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
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Proposed abstract:
Approximate multipliers are widely used in error-tolerant applications such as image processing, digital signal processing, machine learning, edge computing, and energy-efficient computing systems, where a limited reduction in computational accuracy can be accepted to achieve lower power consumption and hardware complexity. Truncation-based approximate multipliers offer simple and scalable architectures; however, the removal of less significant operand information introduces computational error and creates a requirement for effective error compensation. Existing scaleTRIM architecture improves accuracy through segment-based compensation, where the truncated fractional sum is divided into multiple regions and predefined compensation values are applied. Although this technique provides effective error correction, it requires offline error analysis, predetermined compensation values, and additional selection logic, which can increase implementation overhead. To overcome these limitations, this work proposes a Residual-Aware Algorithmic Compensation (RAAC) technique for energy-efficient truncation-based approximate multipliers. Instead of selecting stored compensation values based only on the fractional sum, the proposed method utilizes both the truncated fractional sum and the difference between the truncated operands to capture additional information related to the residual approximation error. The compensation value is generated directly using low-complexity arithmetic and fixed-shift operations, thereby eliminating the conventional segment-based compensation table. The main novelty of the proposed work is the introduction of operand-difference information into an algorithmic compensation mechanism while maintaining a multiplier-free and scalable compensation datapath. The proposed architecture is developed for 8-, 16-, and 32-bit operand widths using synthesizable Verilog HDL and evaluated using the Xilinx FPGA design environment. Hardware performance is evaluated in terms of LUT utilization and power consumption, while approximation performance is characterized using MED, MRED, maximum error, and error standard deviation. The synthesis results show consistent power reduction across the evaluated operand widths, indicating that the proposed RAAC technique is suitable for scalable and energy-efficient approximate computing applications.
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Residual-Aware Algorithmic Compensation for Energy-Efficient Truncation-Based Approximate Multipliers
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Original price was: ₹20,000.00.₹16,000.00Current price is: ₹16,000.00.