A T8T-SRAM Computing-in-Memory Macro for Ternary Deep Neural Networks and Boolean Logic Computations
Original price was: ₹12,000.00.₹8,000.00Current price is: ₹8,000.00.
Source : Tanner EDA
Base paper abstract:
Deep neural networks (DNNs) play important roles in artificial intelligence applications and show hungry computility and power demands. Compared with binary neural networks (BNNs), ternary neural networks (TNNs) have higher representation and adaptive abilities and balance the inference accuracy and computing efficiency between DNNs and BNNs. This article proposed a T8T-SRAM computing-in-memory (CIM) macro to achieve Boolean logic operations and MAC operation of ternary activation and ternary weight. The proposed T8T-SRAM bitcell has a separate read and write path, and can avoid the read disturb issue. In Boolean logic operation mode, the T8T-SRAM macro can achieve NAND, NOR, XNOR, and XOR operations with redundant rows, reducing the additional reference voltage generation circuit. In the MAC mode, the result is quantized by an embedded column analog-to-digital converter (ADC), which uses activation refresh to reduce weight changing. In 28-nm CMOS technology, under 0.5-V array supply voltage and 0.9-V peripheral supply voltage, simulation results manifest that the MAC results have good linearity, and feasibility of Boolean logic operation. The proposed T8T-SRAM macro realizes MAC operation of 16 ternary activations and 16 ternary weights with 333.99–816.1-TOPS/W energy efficiency and 61.9-TOPS/mm2 area efficiency. Using an ResNet-18 network for the inference of MNIST, and CIFAR-10 datasets, the accuracies were 99.06% and 85.76% with a ternary activation and ternary weight.
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Proposed abstract:
Computing-in-Memory (CIM) based SRAM architectures have emerged as a promising solution for artificial intelligence, edge computing, Internet of Things (IoT), and low-power embedded systems by reducing data movement between memory and processing units, thereby improving computational speed and energy efficiency. However, existing SRAM-CIM designs, including recently reported 28 nm implementations, still face challenges such as larger silicon area, increased transistor count, higher power consumption, longer propagation delay, and complex hardware integration for Boolean logic and multiply-and-accumulate (MAC) operations. Although the reported 28 nm T8T-SRAM architecture demonstrated improved computing capability for ternary neural networks, there is still a need for a more compact and power-efficient circuit implementation suitable for future VLSI systems. To address these limitations, this work proposes a compact T8T-SRAM based architecture implemented using 22 nm CMOS technology in the Tanner EDA environment. The proposed work includes the design and implementation of an optimized 8T-SRAM, T8T-SRAM, NAND, NOR, XOR, XNOR, Sense Amplifier (SA), and MAC circuits, forming the essential building blocks for future SRAM-CIM architectures. The novelty of the proposed work lies in implementing these optimized circuit blocks in a smaller 22 nm technology node while reducing hardware overhead and improving circuit compactness compared with the existing 28 nm implementation. The proposed design is prioritized to support future low-power and high-density in-memory computing applications with reduced silicon area and improved hardware efficiency. The circuits were designed, simulated, and verified using Tanner EDA, and their performance was evaluated in terms of layout area, transistor count, propagation delay, and average power consumption. The obtained results demonstrate that the proposed 22 nm implementation provides a compact, reliable, and energy-efficient hardware solution, making it a strong candidate for next-generation SRAM-based computing-in-memory systems and advanced VLSI applications.
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Design and Implementation of a 22nm CMOS T8T-SRAM with Integrated Boolean Logic and MAC Circuit using Tanner EDA
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