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Overflow-Driven Dynamic Precision Scaling Fixed-Point Multiply-Accumulator Unit
Original price was: ₹20,000.00.₹16,000.00Current price is: ₹16,000.00.
Source : Verilog HDL
Base paper abstract:
A novel full-hardware multiply-accumulate (MAC) unit capable of dynamic precision scaling (DPS) and specifically designed for embedded applications is introduced. The MAC autonomously detects and mitigates on-chip overflow and over representation and eliminates the need for any external software controller. A compact run-time monitoring unit (RMU), within each MAC, dynamically monitors the transitions of carry-out and sign bit, and adjusts the operand representation at the bit level so that any rounding error remains bounded by 2−(Nin−1) . Bit-sliced input partitioning enables run-time reconfigurability of operand width and accumulation depth without altering the logic topology. Prototyped on a Xilinx Artix-7 FPGA, the proposed unit achieves up to 14% lower dynamic power and 15% higher maximum clock frequency than a conventional fixed-width MAC with the same precision; in a Skywater CMOS 130 nm, it occupies 3.9 × 103 µm2 , reaches a critical-path delay of 2.68 ns, and consumes 6.07 µW/MHz.
List of the following materials will be included with the Downloaded Backup:
1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Existing and Proposed Project Comparison with output video
3. Basic Documentation (20 to 30 Pages):
3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
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Proposed abstract:
Multiply-accumulate (MAC) units are widely used in digital signal processing, image processing, machine learning, neural network accelerators and other compute-intensive applications, where efficient multiplication and accumulation are important for achieving high processing performance. Fixed-point MAC architectures provide advantages such as lower hardware complexity, reduced power consumption and faster computation compared with floating-point implementations; however, limited accumulator width can introduce overflow, while excessive bit width increases area, power and hardware resource utilization. Existing overflow-driven dynamic precision scaling (ODPS) MAC architectures address this problem by dynamically scaling the accumulated data according to overflow and over-representation conditions, and the existing approach employs a Radix-4 Booth multiplier with asymmetric operand slicing to reduce implementation complexity. However, fixing one operand slice to a small width can limit the flexibility of the multiplication architecture when higher and equal operand precisions are required. To address this limitation, this work proposes the design and analysis of symmetric and asymmetric Booth multiplier architectures integrated with an ODPS MAC. The asymmetric architecture employs Radix-4 Booth multiplication with mixed operand widths of 4×2, 8×2, 16×2, 32×2 and 64×2, whereas the symmetric architecture employs modified Radix-8 Booth multiplication with equal operand widths of 4×4, 8×8, 16×16, 32×32 and 64×64. The novelty of the proposed work is the systematic integration and evaluation of these two Booth multiplication approaches within the same dynamic precision scaling MAC framework, enabling the trade-off between compact asymmetric multiplication and higher-width symmetric multiplication to be studied. The proposed architectures are developed using synthesizable Verilog HDL, functionally verified using ModelSim and synthesized on an Artix-7 FPGA using Xilinx Vivado. Performance is evaluated in terms of LUT utilization, flip-flops, I/O resources, power consumption and timing performance to identify suitable configurations for different precision, hardware-resource and performance requirements.
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Design and Analysis of Symmetric and Asymmetric Booth Multiplier Architectures for Overflow-Driven Dynamic Precision Scaling MAC
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