Design of Low-Power and Area Efficient ECG Low Pass Filter Using VSCP

Objective of This Work

1. To design an ECG-specific low-pass filter suitable for biomedical signal acquisition using 45-nm CMOS technology.
2. To implement the low-pass filter using a vertical source-coupled pair (VSCP) trans-conductance architecture for improved linearity and stability.
3. To adapt and convert an existing VSCP-based EEG low-pass filter architecture for ECG signal bandwidth requirements.
4. To achieve ultra-low power consumption suitable for wearable and long-term ECG monitoring applications.
5. To minimize silicon area by reducing transistor count and simplifying the circuit topology.
6. To optimize biasing conditions to ensure reliable operation under low-voltage and low-power constraints.
7. To preserve essential ECG signal characteristics while effectively suppressing high-frequency noise.
8. To evaluate the frequency response, power dissipation, noise performance, and area through circuit-level simulations.
9. To compare the proposed design with conventional ECG low-pass filter implementations in terms of power and area efficiency.
10. To demonstrate the suitability of the proposed filter for integration into compact, battery-operated biomedical systems using advanced CMOS technology.