Source : Verilog HDL

Cost Only for Simulation: FPGA Board Cost is Additional.

Proposed Abstract:

Electrocardiogram (ECG) signal processing, plays an important role in healthcare applications, including arrhythmia detection, fetal ECG monitoring, heartbeat classification, and cardiac abnormality analysis. Although ECG sensors support real-time signal acquisition, their dependence on physical measurements, signal noise, and patient availability creates limitations during hardware development and testing. Existing FPGA-based ECG processing systems commonly use predefined datasets stored in memory or sensor-based acquisition methods, which may introduce difficulties in dataset loading, memory management, data verification, and repeated testing. To overcome these challenges, this work proposes an FPGA-based ECG dataset transmission, storage, and retrieval architecture using a MATLAB graphical user interface (GUI) and UART communication. The proposed system is implemented on a Xilinx Spartan-6 LX9 FPGA, where 16-bit ECG samples are transmitted from MATLAB through an FT-232R USB-to-UART interface and stored in FPGA Block RAM. A dedicated UART and memory controller manages data writing and reading, while a 2×16 LCD displays transmission status and memory information without interrupting data communication. The stored ECG samples are retrieved through a command-based readback mechanism and plotted in MATLAB for waveform comparison and data verification. The main novelty of this work is the integration of bidirectional ECG dataset communication, memory-controlled storage, command-based retrieval, continuous hardware status monitoring, and GUI-based waveform verification into a reusable FPGA testing platform without requiring physical ECG sensors. The system is evaluated using MATLAB R2018a and FPGA hardware implementation at a UART baud rate of 9600 with 8N2 configuration. Experimental verification demonstrates successful transmission and retrieval of 16,384 ECG samples, corresponding to 32,768 bytes, with 100% data transfer completion and exact byte-level matching. The proposed architecture provides a reliable foundation for future FPGA-based ECG filtering, feature extraction, and cardiac classification applications.

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