A Configurable Floating-Point Fused Multiply-Add Design with Mixed Precision for AI Accelerators

Source : Verilog HDL

Base Paper Abstract:

Hardware accelerators for deep learning in artificial intelligence applications must often meet stringent constraints for accuracy and throughput. In addition to architecture/algorithm improvements, high performance computational techniques such as mixed precision are also required. In this paper, a floating-point (FP) fused multiply-add (FMA) unit supporting mixed/multiple precision is proposed. A wide range of conventional FP formats (such as half and single) as well as emerging formats (including E4M3, E5M2, DLFloat, BFLoat16 and TF32) are supported in the proposed design. In addition to all these formats, the proposed design is flexible in manipulating the exponent and mantissa lengths for 8, 16 and 32-bit FP numbers based on the needs of an application. The proposed FMA can be configured to support either multiple normal FMA operations, or alternatively mixed precision in ASIC. It is fully pipelined and in each cycle, the input bit streams are processed based on the provided configuration, so independent of the previous cycles. For normal FMA operations, the proposed design utilizes sharing of resources to parallelize multiple operations based on the available hardware and required precision. For mixed precision the FMA accumulates the lower precision dot products into higher precision to avoid overflow/underflow. It improves computational accuracy by adding all possible dot products at the same time while decreasing the number of rounding operations to prevent rounding errors. An innovative method to accumulate the dot products and the aligned addend is also proposed. By, considering tradeoffs between reusing the available hardware and removing unnecessary complex units, a more efficient and flexible design is attained in terms of hardware metrics and supported different precision computation compared to other designs found in the technical literature. Extensive simulation results for comparative analysis are provided.

List of the following materials will be included with the Downloaded Backup:

1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)

2. Existing and Proposed Project Comparison with output video

3. Basic Documentation (20 to 30 Pages):

3.1 Proposed Title

3.2 Proposed Abstract

3.3 Advantages & Disadvantages

3.4 Improvement of this Project

3.5 Existing System with Notes

3.6 Proposed System with Notes

3.7 Literature Survey

3.8 Software Related Notes

3.9 VLSI and HDL Language / Tanner Notes

3.10 References & Reference Paper for More Pages

4. Online Support ( Any Desk / Zoom / Google Meet)

Objective of this project:

Develop a flexible hardware FMA unit capable of handling various floating-point (FP) formats — both standard (Half, Single) and emerging (E4M3, E5M2, BFloat16, DLFloat16, TF32).
Enable
Objective of this project:
- Develop a flexible hardware FMA unit capable of handling various floating-point (FP) formats — both standard (Half, Single) and emerging (E4M3, E5M2, BFloat16, DLFloat16, TF32).
- Enable configurability in exponent and mantissa bit widths (from 8- to 32-bit FP numbers) to adapt precision and dynamic range for specific AI applications.
- Support both multiple and mixed-precision operations:
- Multiple precision: Perform several independent FMA operations in parallel (e.g., 4×8-bit, 2×16-bit, or 1×32-bit FMAs).
- Mixed precision: Accumulate several low-precision dot products into higher-precision results to enhance numerical stability and prevent overflow/underflow.
- Improve computational efficiency by reducing rounding steps and resource duplication, thus minimizing hardware area, delay, and power.
- Introduce an innovative accumulation method for dot products and aligned addends that maintains accuracy and reduces rounding errors.
- Achieve better trade-offs between hardware complexity, performance, and accuracy compared to existing FMA architectures.
in exponent and mantissa bit widths (from 8- to 32-bit FP numbers) to adapt precision and dynamic range for specific AI applications.
Support both multiple and mixed-precision operations:
Multiple precision: Perform several independent FMA operations in parallel (e.g., 4×8-bit, 2×16-bit, or 1×32-bit FMAs).
Mixed precision: Accumulate several low-precision dot products into higher-precision results to enhance numerical stability and prevent overflow/underflow.
Improve computational efficiency by reducing rounding steps and resource duplication, thus minimizing hardware area, delay, and power.
Introduce an innovative accumulation method for dot products and aligned addends that maintains accuracy and reduces rounding errors.
Achieve better trade-offs between hardware complexity, performance, and accuracy compared to existing FMA architectures.

Software Implementation:

Modelsim & Vivado

” Thanks for Visit this project Pages – Buy It Soon “