Two Novel Approximate Radix-4 Booth Encoders for Efficient Signed Approximate Booth Multipliers

Improvement of this project:

• The proposed fixed-width multiplier reduces routed LUT utilization by 16.67%–25.00% through selective truncation and partial-product reduction, making it suitable for compact VLSI applications.
• Hybrid Radix-4 Booth encoding and carry-only guard logic reduce the critical path delay by up to 20.06%, supporting faster arithmetic operations in signal and image processing applications.
• The proposed signed boundary compensation technique reduces mean error distance by 33.2%–38.0% compared with uncompensated variants, improving the accuracy of the truncated output. However, further optimization is needed to match the accuracy of existing multipliers.

Proposed Title:

Design and Analysis of an Area-Efficient Fixed-Width Approximate Radix-4 Booth Multiplier Using Selective Truncation and Signed Boundary Compensation

Proposed Abstract:

Approximate multipliers are widely used in digital signal processing, image processing, computer vision, and embedded systems, where reduced hardware complexity and faster computation are important. These multipliers offer advantages in area and delay, but approximation errors and increased power consumption in certain operating conditions remain significant challenges. Existing approximate Radix-4 Booth multipliers use exact encoding in higher-weight columns and approximate encoders and compressors in lower-weight columns to reduce hardware requirements. However, these architectures generate a 16-bit product for 8-bit operands, resulting in additional hardware when only a scaled 8-bit output is required. To address this limitation, this work presents an area-efficient signed fixed-width hybrid Radix-4 Booth multiplier using selective truncation and signed boundary compensation. The proposed architecture divides the partial-product array into three regions, where columns 15–12 use exact Booth logic, columns 11–8 employ AR4BE1 and AR4BE2 approximate encoding with selected compression, and columns 7–0 undergo selective truncation. The lower six columns are eliminated, while columns 6 and 7 retain carry-only guard logic. The main novelty lies in combining retained-column approximation, selective partial-product elimination, and signed Booth boundary estimation to generate an 8-bit product without computing the complete 16-bit result. The proposed designs are developed using Verilog HDL and verified through ModelSim with one million input samples per design. FPGA implementation is performed using Xilinx Vivado 2020.1 targeting an Artix-7 device. Experimental results demonstrate a 16.67%–25.00% reduction in routed LUT utilisation, with delay improvements of up to 20.06% compared with the corresponding existing implementations. Although the proposed architecture introduces higher approximation error and does not consistently reduce dynamic power, it provides a practical area–delay trade-off for fixed-width arithmetic applications.