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An Approximate Digital CIM Macro with Low-Power Multiply-Add Units
Original price was: ₹12,000.00.₹6,000.00Current price is: ₹6,000.00.
Source : Tanner EDA
Base paper abstract:
This letter presents an approximate digital compute-in memory (CIM) macro for low-power edge AI inference. It introduces three hierarchical innovations: 1) novel fused approximate multiply-add units (FAMUs) that reduces power and area consumption; 2) a bit-critical weight allocation architecture that optimally balances accuracy and hardware cost; and 3) a dynamic sparsity-adaptive configuration method to minimize accuracy loss in real-time. The macro achieves an energy efficiency of 60.35 TOPS/W and an area efficiency of 1105 GOPS/mm2 for INT8 MACs, outperforming prior works. It attains negligible accuracy degradation on multiple mainstream datasets and suits well for edge AI inference.
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3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
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Proposed abstract:
Compute-in-Memory (CIM) has become an important architecture for artificial intelligence, edge computing, Internet of Things (IoT), and embedded systems because it performs data processing within the memory array, thereby reducing data movement, execution latency, and energy consumption. Among various CIM approaches, digital approximate CIM provides better reliability than analog CIM while maintaining high computational efficiency. However, conventional digital CIM architectures require separate multiplier and adder circuits, resulting in increased hardware complexity, power consumption, and silicon area. To overcome these limitations, this work introduced a Fused Approximate Multiply-Add Unit (FAMU), which combines multiplication and addition into a single compact circuit to reduce hardware overhead. The work further proposed three FAMU variants, namely FAMU1, FAMU2, and FAMU3, where FAMU1 provides minimum hardware cost, FAMU2 offers improved approximation accuracy, and FAMU3 achieves the highest computational accuracy among the approximate units. These circuits are integrated with a bit-critical weight allocation architecture and a dynamic sparse-adaptive configuration technique to balance computational accuracy and energy efficiency for edge AI inference. In this work, the proposed FAMU1, FAMU2, and FAMU3 architectures are implemented and analyzed using 45 nm CMOS technology at a supply voltage of 0.8 V to evaluate the impact of technology scaling on the original design. The novelty of this work lies in validating the original FAMU architecture under an advanced CMOS process and demonstrating improved hardware performance without modifying its operating principle. The circuits are designed and simulated using the Tanner EDA Tool, and their performance is compared with the reported 55 nm CMOS implementation in terms of power consumption, propagation delay, transistor count, area, and energy efficiency. The obtained results demonstrate that the 45 nm implementation provides lower power dissipation, reduced delay, and improved overall efficiency while preserving the functionality and approximation characteristics of the original FAMU-based compute-in-memory architecture.
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Performance Evaluation of Fused Approximate Multiply-Add-Units using 45nm CMOS Technology for Compute-in-Memory Application
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An Approximate Digital CIM Mac...
Original price was: ₹12,000.00.₹6,000.00Current price is: ₹6,000.00.