Energy-Quality Scalable Adders Based on Non-zeroing Bit Truncation
Original price was: ₹16,000.00.₹8,000.00Current price is: ₹8,000.00.
Source : VHDL / Verilog HDL
Abstract:
Approximate addition is a technique to trade off energy consumption and output quality in error-tolerant applications. In prior art, bit truncation has been explored as a lever to dynamically trade off energy and quality. In this brief, an innovative bit truncation strategy is proposed to achieve more graceful quality degradation compared to state-of-the-art truncation schemes. This translates into energy reduction at a given quality target. When applied to a ripple-carry adder, the proposed bit truncation approach improves quality by up to 8.5 dB in terms of peak signal-to-noise ratio, compared to traditional bit truncation. As a case study, the proposed approach was applied to a discrete cosine transform engine. In comparison with prior art, the proposed approach reduces energy by 20%, at insignificant delay and silicon area overhead.
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Proposed Title :
FPGA Implementation of Non-Zeroing method of 64-Bit Truncated Scalable Adder
Improvement of this Project:
To implement a Truncation Adder using in 8-Bit , 16- Bit, 32- Bit and 64-Bit
Software implementation:
- XILINX & MODELSIM
Proposed System:
In this Emerging technology of paradigm to dynamically reduced the consumption in applications that can naturally tolerate inaccuracies, such as multimedia, machine learning, digital signal processing and wireless communications. In this general area approximate addition has been widely explored and several approximate full adders have been proposed to approximate the least significant output bits (LSBs). In this proposed work will introduced a approximate addition with using Truncation method among many equivalent configurations in least significant bit, thus will reduced energy and increases quality outputs in terms of peak signal to noise ratio. Finally this work will designed in VHDL, synthesized in Xilinx FPGA and compared all the parameters in terms of area, delay and power and also compared with traditional truncation adders.
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Energy-Quality Scalable Adders Based on Non-zeroing Bit Truncation
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