Design Methodology for Voltage Scaled Clock Distribution Networks
Original price was: ₹10,000.00.₹6,000.00Current price is: ₹6,000.00.
Source : TANNER EDA
Abstract:
A low-voltage/swing clocking methodology is developed through both circuit and algorithmic innovations. The primary objective is to significantly reduce the power consumed by the clock network while maintaining the circuit performance the same. a novel D-flip-flop (DFF) cell that maximizes power savings by enabling low-voltage/swing operation throughout the entire clock network . In this proposed design of the LSFF is consume the less power compare to existing design. The proposed architecture of this paper is analysis the logic size, area and power consumption using tanner tool.
List of the following materials will be included with the Downloaded Backup:
Proposed Title :
CMOS Design Methodology on 32 nm Voltage Scaled Clock Distribution Network
Software implementation:
- Tanner EDA
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Design Methodology for Voltage Scaled Clock Distribution Networks
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