Proposed Title:

An Efficient AES-GCM Architecture Using Overlap Free Karatsuba GF(2¹²⁸) Multiplier on Artix-7 FPGA

Proposed Abstract:

Authenticated encryption plays an important role in modern secure communication systems such as IoT devices, wireless networks, cloud storage, embedded systems, and high-speed data transmission applications because it provides both confidentiality and authentication in a single architecture. Among different authenticated encryption schemes, AES-GCM is widely used due to its high security, parallel processing capability, and low latency operation. However, the GHASH module in AES-GCM introduces high computational complexity and critical path delay because of the GF(2¹²⁸) multiplication process, which limits overall throughput and hardware efficiency in FPGA implementations. Existing works mainly focused on conventional Karatsuba Ofman Algorithm (KOA)-based GHASH architectures and pipelined multipliers, but they still suffer from XOR overlap delay, authentication bottleneck, and higher propagation delay in recursive multiplication stages. To overcome these limitations, this work proposes a high-speed AES-GCM authenticated encryption architecture using a 128-bit overlap-free Karatsuba GF(2¹²⁸) multiplier and a parallel KOA GHASH controller for efficient authentication processing. The proposed architecture also integrates Carry Lookahead Adders (CLA) to reduce arithmetic propagation delay in both AES and multiplier datapaths. In this work, 512-bit plaintext data is processed using four sequential AES-128 encryption operations to improve multi-block encryption efficiency. The major novelty of the proposed work is the integration of overlap-free Karatsuba multiplication, parallel GHASH scheduling, and CLA-assisted datapath optimization into a unified FPGA-based AES-GCM architecture for reduced critical delay and improved throughput performance. The complete architecture was designed using Verilog HDL and synthesized in Xilinx Vivado targeting Artix-7 FPGA. Performance evaluation was carried out based on LUT utilization, timing analysis, operating frequency, throughput, and hardware efficiency, where the proposed architecture achieved high-speed operation at 400 MHz with improved timing performance compared with conventional Karatsuba-based AES-GCM implementations.