Proposed Title :
CMOS Implementation of 22nm Low Power and High Performance 4-16 Mixed Logic Line Decoders.
Improvement of this project :
- To implement the design of 2-4 line decoders and new 4-16 decoders are designed, by using mixed-logic 2-4 pre decoders combined with standard CMOS post-decoder.
- Implement this technique in 22nm CMOS technology.
Software implementation:
- Tanner EDA
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Design of Low Power High Performance 2-4 and 4-16 Mixed-Logic Line Decoders
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