An Efficient Approximate Radix-8 Booth Multiplier for Edge Detection

Improvement of this project:

1. Truncated Approximate Radix-8 Booth Multiplier: Develop an optimized Radix-8 Booth multiplier using controlled partial-product truncation to reduce hardware complexity, LUT utilization, and power consumption.
2. Logarithmic Approximation Technique: Incorporate logarithmic approximation into the proposed multiplier to simplify multiplication operations and investigate improvements in computational efficiency.
3. Optimized Partial Product Generation: Reduce the number and complexity of partial products by combining Radix-8 Booth encoding with approximation techniques.
4. Reduced Hardware Area: Minimize FPGA resource utilization, including LUTs, flip-flops, and DSP blocks, compared with conventional Radix-8 Booth multiplier architectures.
5. High-Speed Multiplication: Optimize the partial-product reduction and final addition stages to reduce critical-path delay and improve maximum operating frequency.
6. Low-Power MAC Unit: Integrate the proposed truncated approximate multiplier into an optimized Multiply–Accumulate (MAC) architecture to reduce the hardware overhead of repeated multiplication and accumulation operations.
7. 3×3 Weight-Stationary Systolic Array: Develop a 3×3 systolic array using the proposed MAC units to enable parallel convolution processing and improve data reuse.
8. CNN-Oriented Convolution Architecture: Extend the multiplier from a standalone arithmetic unit to a complete convolution accelerator suitable for CNN-oriented image-processing applications.
9. FPGA-Based Sobel Edge Detection: Implement the proposed architecture for edge detection using 256×256 grayscale images, including biomedical MRI images.
10. Controlled Approximation Error: Balance numerical accuracy and hardware efficiency through selective approximation and truncation, while preserving the significant product information.
11. Three-Multiplier Comparative Analysis: Evaluate conventional Radix-8 Booth, logarithmic Radix-8 Booth, and proposed truncated approximate Radix-8 Booth multipliers under consistent FPGA implementation conditions.
12. Multi-Level Hardware Evaluation: Analyze area, delay, power, frequency, and energy efficiency at three implementation levels: standalone multiplier, MAC unit, and 3×3 systolic array.
13. Arithmetic Accuracy Evaluation: Measure MED, NMED, MRED, and error rate to quantify the computational errors introduced by approximation and truncation.
14. Image Quality Preservation: Evaluate final Sobel edge-detection results using MSE, PSNR, and SSIM to determine how arithmetic approximations affect image quality.
15. End-to-End Hardware–Accuracy Optimization: Establish a direct relationship between multiplier approximation, MAC computation, systolic-array performance, and final image-processing quality.

Proposed Title:

Design of an FPGA Efficient Truncated Approximate Radix-8 Booth Multiplier Based Systolic Array for Sobel Edge Detection

Proposed Abstract:

Convolution-based image processing is widely used in medical imaging, surveillance, autonomous vehicles, robotics, and smart camera systems due to its ability to extract important image features with high processing efficiency. Convolutional Neural Networks (CNNs) provide effective image analysis, but their repeated multiplication and accumulation operations increase hardware area, power consumption, and processing delay in FPGA-based implementations. Conventional Radix-8 Booth multipliers offer accurate computation and reduce partial product generation, but their complex arithmetic operations introduce additional hardware overhead. Existing approximate Booth and logarithmic multiplier architectures reduce computational complexity, although approximation errors may affect the quality of processed images. Moreover, most existing studies focus on standalone multipliers, MAC units, or CNN accelerators, with limited analysis of approximation effects across the complete processing architecture. To address these challenges, this work proposes an FPGA-efficient truncated approximate Radix-8 Booth multiplier incorporating logarithmic approximation and controlled partial product truncation to reduce hardware complexity while preserving significant arithmetic information. The proposed multiplier is integrated into an optimized Multiply–Accumulate (MAC) unit and further developed as a 3×3 weight-stationary systolic array for convolution-based Sobel edge detection using 256×256 grayscale medical images. The novelty of this work lies in the unified multiplier-to-MAC-to-systolic-array architecture and the systematic investigation of how arithmetic approximation influences hardware efficiency and final image quality. The proposed design will be developed using Verilog HDL, verified through functional simulation, and synthesized using Xilinx Vivado for FPGA implementation. Hardware performance will be evaluated using LUTs, flip-flops, DSP utilization, power, delay, maximum operating frequency, and energy efficiency. Computational accuracy and image quality will be assessed using MED, NMED, MRED, error rate, MSE, PSNR, and SSIM, with comparisons against conventional and logarithmic Radix-8 Booth architectures.