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A Counter Based Addition Circuit Design for Stochastic Computing
Original price was: ₹12,000.00.₹6,000.00Current price is: ₹6,000.00.
Source : Verilog HDL
Base paper abstract:
Stochastic computing (SC) encodes real values via probabilistic bitstreams, enabling complex arithmetic operations to be realized by simple logic gates. However, the requirement of longer bitstreams to ensure computing accuracy leads to higher latency, partially offsetting the low-complexity advantage of SC. To address this, this work utilizes a dynamic truncation method for stochastic bitstreams, and designs an energy-efficient counterbased addition circuit (CBAC) through effective bit recognition and correlation. Further, a tree-structured cascading architecture is then used to perform multi-input addition computing. Experimental results demonstrate that the proposed CBAC outperforms the state-of-the-art designs. For instance, a 16-input configuration achieves at least 75.9% reduction in mean square error (MSE) and a more than 43.1% reduction in area. When applied to polynomial computation and Gaussian filtering, the proposed architecture exhibits superior accuracy and efficiency, delivering MSE reductions of at least 10.7% and area reductions exceeding 6.8%.
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3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
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3.10 References & Reference Paper for More Pages
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Proposed abstract:
Convolutional Neural Networks (CNNs) have become one of the most widely adopted deep learning techniques for image processing, object detection, medical imaging, autonomous systems, and intelligent edge devices. However, conventional CNN hardware implementations require multiple binary multipliers, wide adders, and divider circuits to perform convolution and mean operations, resulting in high logic utilization, increased power consumption, and longer critical paths. For example, an 8-bit 3×3 convolution requires nine multipliers that generate 16-bit products, followed by large multi-input addition and division circuits, significantly increasing hardware complexity. Stochastic computing provides an attractive alternative by replacing complex arithmetic units with simple logic circuits, thereby reducing hardware cost and improving fault tolerance. In this work, the N-input Counter-Based Addition Circuit (CBAC) architecture is employed as an efficient hardware building block for CNN convolution operations. The proposed implementation demonstrates support for both 2×2 and 3×3 CNN kernels using the same scalable CBAC architecture, eliminating the need for conventional binary adders and divider circuits during mean-value computation. The architecture is designed in Verilog HDL and synthesized on a Xilinx Virtex-5 FPGA to evaluate hardware resource utilization, logic performance, operation cycles, propagation delay, and power consumption. Experimental results show that the proposed CBAC-based CNN architecture significantly reduces hardware complexity while maintaining efficient timing performance and low power consumption. The architecture provides a compact and scalable solution for stochastic CNN accelerators, making it suitable for low-power, high-performance edge intelligence applications.
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Design and FPGA Implementation of a Scalable Counter Based Addition Circuit for 3×3 CNN Architecture
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A Counter Based Addition Circu...
Original price was: ₹12,000.00.₹6,000.00Current price is: ₹6,000.00.