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Approximate Multiplier for Power Efficiency in FPGA Design Using Internal Self-Healing
Original price was: ₹12,000.00.₹8,000.00Current price is: ₹8,000.00.
Source : Verilog HDL
Base paper abstract:
Approximate Computing has emerged as a viable solution to resource constraints in computing for error-resilient applications by relaxing accuracy for significant gains in terms of power, performance, and area. Among existing approximation techniques, the self-healing methodologies have shown a promising quality-efficiency balance by canceling out the overall effect of computational errors. However, they rely on highly parallel implementations for error cancellation. In our prior work (MACISH), we proposed an Internal-Self-Healing (ISH) methodology that applies approximations in the recursive multiplication stage and leverages the accumulation stage for error cancellation, eliminating the need for paired parallel modules required by traditional self-healing approaches. ASIC-based digital designs proposed by MACISH demonstrated superior quality-efficiency results for the radio astronomy application. However, the architectural differences limit the direct mapping of ASIC-based optimized designs to FPGAs. Therefore, this article addresses the gap by designing the FPGA-based Pareto-optimal 4-bit and 8-bit recursive approximate multipliers using ISH methodology. The proposed Design Space Exploration (DSE) strategy manages the vast 8-bit design space by deriving the candidate designs from 4-bit Pareto-optimal multipliers, reducing the search complexity while preserving the performance. The proposed designs achieve up to 12% and 33.6% better power and energy efficiency, respectively, compared to accurate 8-bit multipliers and up to 30× improved output quality at a similar area. The design flow is automated using the ‘Approxy’ Tool, which has also been developed as part of this work. For the radio astronomy correlation application, these designs achieved comparable (and acceptable) output quality with respect to the state-of-the-art. For Deep Learning (DL) workloads, the proposed 8-bit designs matched or even exceeded the baseline accuracy for binary and multiclass classification problems.
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3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
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3.10 References & Reference Paper for More Pages
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Proposed abstract:
Approximate multipliers have become an important solution for modern digital signal processing, image processing, artificial intelligence, machine learning, multimedia, and edge computing applications, where a small loss in computational accuracy is acceptable in exchange for significant improvements in hardware efficiency. These multipliers offer lower power consumption, reduced hardware utilization, shorter critical path delay, and higher operating speed compared to accurate multipliers. However, the reduction in circuit complexity often increases computational error, which limits their adoption in applications requiring a balanced trade-off between accuracy and hardware efficiency. Several recursive approximate multiplier architectures have been reported in the literature, including FPGA-based Internal Self-Healing (ISH) designs that primarily investigate selected 4-bit and 8-bit recursive configurations. Nevertheless, the available work mainly focuses on power-optimized 8-bit implementations and does not comprehensively explore area-optimized recursive configurations or demonstrate scalability towards higher bit-width architectures. To address these limitations, this work designs and verifies five approximate 2-bit multipliers (M1–M5) and develops recursive 4-bit multiplier architectures using both Table 3 and Table 4 configurations. The best-performing 4-bit designs are further employed to construct optimized 8-bit recursive multipliers, followed by a comparative analysis of area-optimized and power-optimized architectures. As the major contribution of this work, the most efficient and lowest-error 8-bit multipliers are recursively utilized to develop a novel 16-bit approximate multiplier, demonstrating the scalability of the proposed methodology while maintaining improved hardware efficiency and computational accuracy. The proposed architectures are evaluated in terms of LUT utilization, power consumption, propagation delay, operating frequency, error metrics, and overall hardware efficiency. Functional verification and performance analysis are carried out using Verilog HDL on the Xilinx ISE design environment targeting the Xilinx Virtex-5 FPGA, where the proposed recursive architecture demonstrates an improved balance between resource utilization, speed, power consumption, and approximation error.
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Design and Implementation of a Recursive 16-bit Internal-Self-Healing Approximate Multiplier for FPGA Applications
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