Design and analysis of Reversible Approximate Full Adder and its applications with Optimized 4:2, 5:2, 7:2 Compressors for Efficient Approximate Multipliers

Source : Verilog HDL

List of the following materials will be included with the Downloaded Backup:

1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)

2. Existing and Proposed Project Comparison with output video

3. Basic Documentation (20 to 30 Pages):

3.1 Proposed Title

3.2 Proposed Abstract

3.3 Advantages & Disadvantages

3.4 Improvement of this Project

3.5 Existing System with Notes

3.6 Proposed System with Notes

3.7 Literature Survey

3.8 Software Related Notes

3.9 VLSI and HDL Language / Tanner Notes

3.10 References & Reference Paper for More Pages

4. Online Support ( Any Desk / Zoom / Google Meet)

Improvements:

To design a novelty design of PERES and Feynman gate based Approximate Full adder in Reversible method, it will help to reduce more number of logic size compared to the existing method.
To compared existing approximate reversible full adder design of RAFA-1 and RAFA-2 for analysis, and proved the performance. RAFA-1 contains three Feynman Gate, and RAFA-2 contains 2 Feynman gate.
In the proposed design PERES Gate and One Feynman Gate design. For this changes, the error rate mostly arrests in the approximate technique.
To design a Multiplier which using 4:2, 5:2, 7:2 compressors and proved the performance of this three design of full adder with exact method with the compressor design with these full adders.

Proposed abstract:

Approximate and reversible computing are increasingly used in low-power signal processing, medical imaging, and machine learning applications, where small inaccuracies can be accepted to achieve reductions in power, area, and delay. These methods offer more advantages such as lower switching activity and reduced heat dissipation in approximate method, but they also face limitations including error accumulation and the need for efficient alternative structure, thus this work design using reversible gate structures to keep logic cost minimal. Existing reversible approximate full adders have lot of design, but it will present with more error analysis. This projects aims to design a error reduction in reversible approximate full adder with lower cost and controlled error behavior. For, that this work, present with a new approximate full adder which using only one PERES gate and one Feynman gate is introduced to reduce the number of reversible gates, constant inputs, and garbage outputs while confining approximation to the least-probable input combination to avoid major error propagation. Existing examples of RAFA-1 and RAFA-2 based reversible adder designs are used for comparison to highlight the improvements in logic size and error rate. Additionally, this design also developed a proposed adder to build reversible 4:2, 5:2, and 7:2 compressors and an approximate multiplier architecture, allowing evaluation of how the new full adder behaves inside higher-order arithmetic blocks. The entire design is described in Verilog HDL, functionally verified using ModelSim, and synthesized on a Xilinx FPGA to measure LUT usage, slice registers, delay, and overall hardware efficiency.

Software Implementation:

Modelsim & Xilinx

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