Hardware Implementation of Improved Banker’s Fixed-Point Rounding Algorithm

Proposed Abstract:

The acceleration of convolutional neural networks (CNNs) on resource-constrained platforms such as FPGAs is critical for emerging applications in image processing, embedded vision, and edge AI. Traditional Winograd convolution algorithms have been widely adopted to reduce the number of arithmetic operations in CNNs. However, their reliance on both input and output matrix transformations imposes substantial logic and resource overhead, limiting their hardware efficiency. In this work, we propose a novel FPGA architecture for Winograd convolution that introduces a lightweight output transform while completely eliminating the input transform stage. This innovation significantly reduces the area and power consumption of the convolution module, enabling more efficient deployment of deep learning workloads in edge devices. The proposed method leverages a simple averaging-based output transform to preserve computational accuracy with minimal hardware resources. We present architectural details, resource utilization analysis, and image quality metrics such as PSNR, SSIM, and MSE to demonstrate the practicality and effectiveness of the approach. This work provides a promising solution for real-time, area-constrained CNN inference on FPGA platforms and sets the stage for future exploration of optimized convolution architectures in low-power and embedded applications.