Scalable AXI4 Transaction Monitoring for Mixed-Criticality SoCs: From Phase-Level Precision to ID-Level Efficiency
Scalable AXI4 Transaction Monitoring for Mixed-Criticality SoCs: From Phase-Level Precision to ID-Level Efficiency
Abstract
Mixed-criticality systems-on-chip (SoCs) with onchip interconnects based on the Advanced eXtensible Interface 4 (AXI4) open standard protocol lack a protocol-level timeout mechanism, exposing systems to deadlocks and missed real-time deadlines when subordinate devices or managers fail or stall due to hardware faults, radiation-induced upsets, or software errors. This work presents a configurable hardware intellectual property (IP), nonintrusive in fault-free operation, that detects AXI4 protocol violations and timing faults at runtime and restores interconnect liveness through a cut-and-drain isolation mechanism. To address the fundamental tradeoff between monitoring granularity and area cost, we introduce three designs at decreasing monitoring granularity: phase-level tracking (PLT), which provides cycle-accurate fault localization across individual protocol phases; channel-level tracking (CLT), which coalesces per-phase monitors into channel-level supervision; and ID-level tracking (ILT), which achieves sublinear area scaling by monitoring only per-ID transaction boundaries. Synthesized in GlobalFoundries 12-nm technology, CLT reduces area by 36.7% relative to PLT while preserving worst case detection bounds at a minimal detection latency overhead, whereas ILT achieves an 89.2% area reduction suitable for tightly constrained deployments at the cost of a 3.7× higher median detection latency with coarser fault localization. Fault injection campaigns on a RISC-V SoC across 1.2 million scenarios confirm that no fault manifesting as an AXI4 protocol or liveness violation escaped detection, with observed detection latencies consistently bounded by theoretical worst case predictions.
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