We propose a novel balise telegram decoding scheme for RFID-based high-speed train protection systems. To reduce the amount of position errors by minimizing the decoding latency, the proposed scheme enables the decoder to have opportunities to find a valid telegram during single balise passage by reutilizing the values from previous failures. We also present a modified linear-feedback shift register (LFSR) and parallel connection of LFSR units to complete both error detection and synchronization of telegrams in one cycle. The experimental results show that the proposed scheme achieves approximately 2,000 times faster error detection and synchronization than traditional architectures.
Software Implementation:
Xilinx 14.2
Advantages:
Less Speed in Decoding process,
Having less electromagnetic interference and crosstalk
