Objective of this work:
- Three MARCH algorithm variants namely MARCH SS, MARCH SR, and MARCH SR+ are successfully implemented and verified within the proposed FIFO-based MBIST architecture.
- A novel FIFO and comparator based pipelined MBIST architecture is proposed that integrates MARCH SS, MARCH SR, and MARCH SR+ algorithms enabling real-time test response validation and seamless switching between test mode and functional mode without additional memory access latency.
- Among the three implemented algorithms, MARCH SR+ achieves the lowest timing delay of 5.54 nanoseconds, MARCH SS achieves 5.611 nanoseconds, and MARCH SR records 5.761 nanoseconds on Xilinx Artix-7 FPGA, demonstrating the timing efficiency of the proposed implementations.
- A comprehensive multi-dimensional comparative fault analysis of MARCH SS, MARCH SR, and MARCH SR+ covering fault coverage, logic utilization, timing delay, static power, and simulation efficiency is performed and validated in ModelSim, providing a complete performance evaluation framework for embedded memory testing in safety-critical VLSI application.
Proposed abstract:
Embedded memory systems based on static random access memory are the computational foundation of modern digital platforms including real-time edge inference engines, autonomous vehicle controllers, aerospace fault-tolerant processors, and industrial internet-of-things devices, where uninterrupted reliability and high data integrity are critical operational requirements. These applications benefit significantly from on-chip memory integration, yet remain highly vulnerable to manufacturing-induced defects such as stuck-at faults, transition faults, coupling faults, read disturb faults, and delay faults that emerge from process variation, voltage scaling, and increasing cell density in advanced CMOS technologies. Conventional March-based memory built-in self-test architectures provide deterministic fault detection but frequently fail to simultaneously address complex coupling-type faults while maintaining compact hardware overhead and low power consumption within an integrated controller structure. Existing implementations of MARCH SS and MARCH SR methods, though functionally valid, demonstrate reduced fault activation capability for deceptive read disturb and idempotent coupling faults, and do not incorporate a unified FIFO and comparator based test architecture that can pipeline test patterns and response verification within the same datapath. To address these limitations, this work proposes a FIFO and comparator based memory built-in self-test architecture designed, simulated, and synthesized on the Xilinx Vivado tool targeting the Artix-7 FPGA platform, where the proposed test circuit implements MARCH SS, MARCH SR, and the proposed MARCH SR plus algorithm as the core test engine for comparative evaluation. The FIFO-based datapath efficiently buffers address and data streams while the comparator module validates memory responses against expected values in real time, enabling pipelined fault detection without additional operational latency. Synthesis results on the Artix-7 FPGA confirm that MARCH SR plus consumes 235 LUTs and 327 flip-flops with the lowest timing delay of 5.54 nanoseconds and a static power consumption of 0.131 watts, while fault simulation results verified in ModelSim demonstrate a total fault detection count of 5198 with the highest fault coverage of 88.89 percent across seven fault categories including stuck-at, transition, coupling, address decode, read disturb, delay, and bridging faults, validating the proposed FIFO-based MBIST architecture as a high-coverage and timing-efficient embedded memory testing solution suitable for safety-critical VLSI applications in artificial intelligence hardware, high-performance computing, and real-time embedded control systems.
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FIFO Based Memory BIST Architecture Using Optimized MARCH Algorithm for High Fault Coverages and Low Power VLSI Testing
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