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Enhancing Memory BIST with an Optimized RTL-BIST IP Core: A Low-Power, High-Fault-Coverage Approach
Original price was: ₹16,000.00.₹12,000.00Current price is: ₹12,000.00.
Source : Verilog HDL
Base paper abstract:
The increasing density of static random access memory (SRAM) in modern system-on-chip (SoC) architectures has intensified the need for efficient built-in self-test (BIST) solutions to ensure fault detection and repair. This article presents an optimized register transfer level (RTL)-BIST intellectual property core (IP core) that integrates a novel March mSR+ algorithm, providing a low-power, high-fault-coverage approach to embedded memory testing. Developed using high level synthesis (HLS), the proposed framework enhances test efficiency while minimizing hardware complexity. Experimental results on field-programmable gate array (FPGA) implementations demonstrate that the March mSR+ algorithm achieves an 88.89% fault coverage while reducing power consumption compared with conventional March-based testing methods. These findings validate the effectiveness of the RTL-BIST framework in improving memory reliability for artificial intelligence (AI), high performance computing (HPC), and safety-critical applications.
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3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
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Proposed abstract:
Embedded memory systems based on static random access memory are the computational foundation of modern digital platforms including real-time edge inference engines, autonomous vehicle controllers, aerospace fault-tolerant processors, and industrial internet-of-things devices, where uninterrupted reliability and high data integrity are critical operational requirements. These applications benefit significantly from on-chip memory integration, yet remain highly vulnerable to manufacturing-induced defects such as stuck-at faults, transition faults, coupling faults, read disturb faults, and delay faults that emerge from process variation, voltage scaling, and increasing cell density in advanced CMOS technologies. Conventional March-based memory built-in self-test architectures provide deterministic fault detection but frequently fail to simultaneously address complex coupling-type faults while maintaining compact hardware overhead and low power consumption within an integrated controller structure. Existing implementations of MARCH SS and MARCH SR methods, though functionally valid, demonstrate reduced fault activation capability for deceptive read disturb and idempotent coupling faults, and do not incorporate a unified FIFO and comparator based test architecture that can pipeline test patterns and response verification within the same datapath. To address these limitations, this work proposes a FIFO and comparator based memory built-in self-test architecture designed, simulated, and synthesized on the Xilinx Vivado tool targeting the Artix-7 FPGA platform, where the proposed test circuit implements MARCH SS, MARCH SR, and the proposed MARCH SR plus algorithm as the core test engine for comparative evaluation. The FIFO-based datapath efficiently buffers address and data streams while the comparator module validates memory responses against expected values in real time, enabling pipelined fault detection without additional operational latency. Synthesis results on the Artix-7 FPGA confirm that MARCH SR plus consumes 235 LUTs and 327 flip-flops with the lowest timing delay of 5.54 nanoseconds and a static power consumption of 0.131 watts, while fault simulation results verified in ModelSim demonstrate a total fault detection count of 5198 with the highest fault coverage of 88.89 percent across seven fault categories including stuck-at, transition, coupling, address decode, read disturb, delay, and bridging faults, validating the proposed FIFO-based MBIST architecture as a high-coverage and timing-efficient embedded memory testing solution suitable for safety-critical VLSI applications in artificial intelligence hardware, high-performance computing, and real-time embedded control systems.
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FIFO Based Memory BIST Architecture Using Optimized MARCH Algorithm for High Fault Coverages and Low Power VLSI Testing
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