High-Throughput RTL Design of a Streaming ZP-OTFS Wideband Channel Estimator
High-Throughput RTL Design of a Streaming ZP-OTFS Wideband Channel Estimator
Abstract
This paper presents a low-complexity, resourceefficient streaming architecture for Channel Estimation in Zero-Padded Orthogonal Time Frequency Space (ZP-OTFS) systems. Building on an established guard-based linear interpolation algorithm, the novelty of this work lies in its streaming hardware architecture: the proposed design reconstructs the channel impulse response in the delay-time domain through a partially parallel interpolation scheme, enabling continuous processing while exploiting the sparsity of the OTFS channel matrix to reduce computational overhead. The architecture is described at the RTL level in VHDL and validated through FPGA-in-the-Loop experiments on an AMD ZCU111 board. Experimental results show a latency of 44.10 µs, a dynamic power consumption of 17 mW, and an energy cost of 1.45 µJ per frame, confirming the feasibility of real-time and power-efficient OTFS channel estimation in high-mobility scenarios. The fixed-point implementation closely matches the floating-point reference, with only slight BER degradation for QPSK, 16-QAM, and 64-QAM. REPN and EVM are evaluated for EPA, EVA, and ETU, while REPN is also reported for UHM, where degradation is attributed to a Doppler phase-rotation validity limit. An ASIC-oriented 16nm FinFET assessment further indicates that the logic-only post-layout result reports 52,093 placed instances, 26,384.590 µm2 of standard-cell area, and 173.72 mW total power at 1 GHz and 0.88 V. These results confirm that the design is suitable for integration into fully hardware-based OTFS receivers.
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