FPGA Deployment of Extremely Quantized Models for Time-to-Lane-Change Prediction
FPGA Deployment of Extremely Quantized Models for Time-to-Lane-Change Prediction
Abstract
Despite the rapid evolution of automated driving, public information about deployability in production vehicles remains limited. We present a Field Programmable Gate Array (FPGA) prototyping study of an AI module for estimating timeto-lane-change (TTLC), focusing on key deployment metrics such as latency, memory footprint, and power/energy consumption. FPGAs enable custom acceleration while providing flexibility to explore multiple design trade-offs. Particularly, we investigate different quantization strategies, given their potential to substantially reduce model size while preserving predictive performance. This brief makes four main contributions that advance the state-of-the-art through an FPGA-based implementation. We present a hardware-aware FPGA design methodology that balances memory efficiency and task accuracy. We provide a comprehensive analysis of the trade-offs achievable by varying AI model type, operating frequency, and quantization precision. We find a set of Pareto-optimal solutions along the power-latency axes, identifying a clear elbow at a co-processor frequency of 25/50 MHz depending on model and quantization type. We implement a Transformer architecture that preserves state-ofthe-art TTLC predictive performance while meeting the 10 Hz real-time constraint and reducing total energy consumption by 83% compared to a high-end microcontroller.
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