Fully Homomorphic Encryption (FHE) is a promising technology that allows calculations to be performed on encrypted data. However, its widespread adoption is hindered by high computational requirements. In this brief, we present a design-time flexible FPGA accelerator that aims to speed up the Number Theoretic Transform (NTT), the most crucial bottleneck in FHE schemes. Our accelerator is throughputoriented and implements a Multipath Delay Commutator (MDC) approach. While previous works focus on radix-2 implementations, we implement a parallel radix-4 NTT architecture. We exploit constants within radix-4 structures and reduce DSP slice utilization by more than 25%. We achieve that by using a recent constant modular multiplication technique by Bertels et al. and leverage special properties of goldilock primes. The polynomial degree, modulus and number of parallel compute cores are design-time configurable. Due to its configurability, our design allows for the evaluation of different area and speed tradeoffs and targets various parameter sets and requirements. To demonstrate the applicability of our approach, we conduct a case study and evaluate different configurations and parameters that are applicable to FHE schemes such as CGGI or CKKS. All implementations are done on the AMD Alveo U55C. Compared to our reference software implementation based on OpenFHE, we achieve a speed-up of up to 23.75×. Compared to related works, with the same bandwidth requirements, we achieve up to 3.81× lower ATP and up to 4.33× higher TPS.
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