Design Space Exploration of a Unified FPGA Accelerator for Elliptic-Curve-Based Functions in Attribute-Based Encryption
Design Space Exploration of a Unified FPGA Accelerator for Elliptic-Curve-Based Functions in Attribute-Based Encryption
Abstract
Attribute-based encryption (ABE) requires several elliptic-curve-based functions, including elliptic-curve scalar multiplication (ECSM), hashing to the curve, and pairing. Although these computations share underlying similarities, prior hardware designs have shown that distinct architectures yield better performance for each function. Consequently, it remains unclear which architecture offers optimal performance when supporting all required functions within a unified design. In this work, we present a design space exploration methodology in which the design is parameterized using a defined set of design parameters, and an automatic schedule generator is employed to estimate the cycle counts for each function. This allows us to identify the configuration that minimizes latency for both individual functions and complete cryptographic operations. The versatility of our approach is demonstrated through two case studies: 1) ECSM over Curve25519, Secp256k1, NIST-P256, and NIST-P384; and 2) multiple elliptic-curve functions over the BLS12-381 curve. In the first case, the optimal configuration implemented on a Virtex7 field-programmable gate array (FPGA) achieves up to a 15% latency reduction compared to state-of-the-art designs. In the second case, the unified accelerator in its optimal configuration supports all core ABE functions and achieves superior latency or throughput-per-area (TPA), and in some cases both, compared to existing designs.
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