An Efficient VLSI Architecture for Hammerstein-Type Spline Adaptive Filters
An Efficient VLSI Architecture for Hammerstein-Type Spline Adaptive Filters
Abstract:
The Hammerstein spline adaptive filter (HSAF) is a class of nonlinear adaptive filters (NAFs), known for its flexible nonlinear modeling and low complexity in applications, such as self-interference cancellation in wireless communications. This brief proposes a delayed dual-weight update reformulation for the HSAF and its efficient high-throughput and low-power architecture. We also propose hardware-efficient techniques for mapping spline interpolation and updating the spline control points in HSAF. The proposed delayed HSAF (DHSAF) architecture is synthesized using Cadence Genus in 45-nm CMOS technology. Synthesis results show that the proposed DHSAF achieves significantly higher throughput compared to the basic HSAF, with only minimal area and power overhead. Furthermore, the proposed DHSAF outperforms the state-of-the-art RFF-KLMS architecture in terms of both area and power efficiency.
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An Efficient VLSI Architecture for Hammerstein-Type Spline Adaptive Filters
