An Efficient Fault-Tolerance Design for Integer Parallel Matrix–Vector Multiplications
[/vc_column_text][vc_column_text] Abstract:
Parallel matrix processing is a typical operation in many systems, and in particular matrix–vector multiplication (MVM) is one of the most common operations in the modern digital signal processing and digital communication systems. This paper proposes a fault tolerant design for integer parallel MVMs. The scheme combines ideas from error correction codes with the self-checking capability of MVM. Field-programmable gate array evaluation shows that the proposed scheme can significantly reduce the overheads compared to the protection of each MVM on its own. Therefore, the proposed technique can be used to reduce the cost of providing fault tolerance in practical implementations.
Software Implementation:
Modelsim
Xilinx 14.2
Advantages:
Overheads are reduced
Cost is low
Error can be easily identified by error detection method
