An Area-Efficient Synthesizable Inverter-Delay-Ring Time-to-Digital Converter With Enhanced Linearity
An Area-Efficient Synthesizable Inverter-Delay-Ring Time-to-Digital Converter With Enhanced Linearity
Abstract
A fully synthesizable, area-optimized time-to-digital converter (TDC) with improved linearity is described. Its architecture exploits a cyclic inverter-based delay line (ring) tapped with two alternating cycle counters. A compact delay ring enables reduced hardware cost and efficient digital post-processing. The delay ring linearity is enhanced through back-annotated insertion of optional dummy inverter capacitive loads. To estimate the average inverter propagation delay, a straightforward calibration scheme is proposed. The TDC prototype fabricated in 180 nm CMOS occupies 4500 µ m2 and consumes a mean power of 2.7 mW at 1.8 V and room temperature. It achieves 52 ps resolution over a 3.2 ns full-scale range, with maximum DNL/INL of 0.38/0.7 LSB and measured single-shot precision of up to 16 ps or 0.31 LSB. Due to its low complexity, excellent PPA, and automated standard-cell-based implementation, the presented architecture is suitable for applications that require numerous digital timing channels.
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