An Area-Efficient Fractional Output Divider Based on Foreground DTC INL Calibration
An Area-Efficient Fractional Output Divider Based on Foreground DTC INL Calibration
Abstract:
This brief presents a fractional output divider (FOD) with a foreground digital-to-time converter (DTC) INL calibration scheme. This calibration scheme adjusts the delay control words of two main DTCs (mDTCs) to enable mutual comparison between them. By using a sign-least-mean-squares (sign-LMS) algorithm, the INL error codes are obtained and subsequently applied to a calibration DTC (cDTC) to compensate for the mDTC INL. The prototype occupies a compact core area of 0.01mm2 and operates at a 0.9V supply with a power consumption of 3.6mW at 500MHz. Measurements demonstrate an integrated jitter of 512fs (10kHz to 20MHz) and spur level of -70dBc at 123.46MHz.
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An Area-Efficient Fractional Output Divider Based on Foreground DTC INL Calibration
