Joint Telemetry Modulation Scheme with LDPC Coding-based 16QAM-COFDM for the Aerospace Telemetry System

Improvement of this project:

• Frame Synchronization: Implemented hardware-based automatic frame detection using a 32-sample PN preamble.
• Payload Buffering: Introduced a 160-sample payload buffer for organized data transmission.
• Preamble Insertion: Added a 32-sample PN preamble after quadrature up conversion for reliable frame identification.
• Complex Correlation: Implemented a normalized complex correlator for preamble detection using received I/Q samples.
• Hardware Optimization: Used a rolling energy accumulator to reduce correlation computation complexity.
• Frame Boundary Detection: Generated internal frame-start markers for accurate demodulation.
• Receiver Buffering: Introduced a frame buffer to capture and process the received payload.
• Fixed-Point Architecture: Developed synthesizable fixed-point arithmetic for FPGA implementation.
• Memory Optimization: Defined structured memory organization and controllers for efficient hardware processing.
• FPGA Implementation: Successfully completed synthesis and implementation with positive timing slack in Vivado 2020.1.
• Low Resource Utilization: Achieved 1.37% LUT utilization for TX and 5.88% for RX.
• Low Estimated Power: Obtained estimated on-chip power of 153 mW for TX and 178 mW for RX.

Objective of this work:

The main objective of this work is to design and implement a hardware-efficient LDPC-based 16QAM-COFDM transceiver using Verilog HDL on an FPGA, incorporating PN preamble-based automatic frame synchronization, normalized complex correlation, and rolling energy accumulation to reduce hardware complexity. The proposed architecture aims to achieve reliable data transmission, accurate frame detection, efficient resource utilization, low power consumption, and timing-efficient operation for aerospace telemetry communication systems.

Proposed Title:

Design and FPGA Implementation of a Hardware-Efficient LDPC-Coded 16QAM-COFDM Transceiver with PN-Based Frame Synchronisation

Proposed Abstract:

LDPC-coded 16QAM-based Coded Orthogonal Frequency Division Multiplexing (COFDM) is widely used in wireless communication, satellite communication, and aerospace telemetry systems due to its high spectral efficiency, improved error correction capability, and reliable data transmission under noisy channel conditions. However, the increased hardware complexity, synchronization errors, memory requirements, and power consumption create challenges for real-time FPGA implementation. Existing LDPC-based 16QAM-COFDM architectures mainly focus on improving bit error rate and transmission reliability through channel coding and multicarrier modulation, while practical hardware-level frame synchronization and efficient resource management require further attention. To address these challenges, this work proposes a hardware-efficient FPGA architecture for an LDPC-coded 16QAM-COFDM transceiver with PN preamble-based automatic frame synchronization. The proposed transmitter integrates LDPC encoding, 16QAM mapping, IFFT processing, cyclic prefix insertion, and quadrature up-conversion, followed by buffering of a 160-sample payload and insertion of a 32-sample PN preamble. At the receiver, a normalized complex correlator detects the preamble directly from the received I/Q samples and controls frame buffering and subsequent demodulation. The main novelty of this work lies in the hardware-oriented integration of PN-based frame detection with a rolling energy accumulator to reduce repeated energy computations, along with fixed-point arithmetic, structured memory organization, and dedicated control logic. The complete architecture is developed using Verilog HDL and implemented on an FPGA using Xilinx Vivado 2020.1. Post-implementation results show LUT utilization of 1.37% and 5.88%, with estimated power consumption of 0.153 W and 0.178 W for the transmitter and receiver, respectively. Both architectures achieve positive timing slack with no failing setup endpoints, demonstrating the feasibility of the proposed design for FPGA-based aerospace telemetry applications.