Polynomial Debugging and Fault Correction of Combinational Circuits With Constant Cutwidth
Polynomial Debugging and Fault Correction of Combinational Circuits With Constant Cutwidth
Abstract
Formal Verification (FV) is a widely used technique for verifying whether a gate-level design is functionally equivalent to its specification. However, when verification fails due to the presence of faults, Debugging and Fault Correction (DFC) becomes essential to localize bugs and correct them. Despite the success of various automatic DFC approaches, existing methods often lack theoretical guarantees on the computational resources required, making them unpredictable in terms of time and space complexity. Therefore, it is essential to establish upper bounds on the time and space complexity of the DFC process to ensure its practical feasibility. In this paper, we rely on the CutWidth (CW) property to introduce Polynomial Debugging and Fault Correction (PDFC) as a subclass of DFC for combinational circuits, where the time and space complexities of DFC are characterized by CW. Specifically, we show that for circuits with bounded CW, the entire DFC process can be polynomially bounded, unlike Yosys SAT, which has exponential complexity. Moreover, we prove that for circuits with constant CW, the entire DFC process can be carried out in linear time and space. Finally, we evaluate several architectures of adders with small constant cutwidth, considering various numbers and locations of faulty gates in terms of time and space required for the DFC process to confirm our theoretical findings and also compare it with Yosys SAT. To demonstrate that our PDFC approach is not limited to adders and can be applied to any design with bounded cutwidth, we also evaluate benchmark circuits from ITC’99 and IWLS’93 in terms of time and space of the DFC process.
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