Pseudo-Dynamic AOI and OAI Standard-Cell-Based Comparators
Pseudo-Dynamic AOI and OAI Standard-Cell-Based Comparators
Abstract
This work introduces a pseudo-dynamic design methodology for fully synthesizable standard-cell-based comparators, accompanied by a compact transistor-level model, in subthreshold region, for delay and power estimation. Two non-rail-to-rail input common-mode range (ICMR) topologies, implemented with AOI (and-or-invert) and OAI (or-and-invert) gates, are proposed. Compared with existing dynamic standardcell-based comparators, the proposed designs achieve higher speed and lower power consumption, while remaining only marginally slower than the best-performing rail-to-rail solution at 150 mV. Post-layout simulations referring to a 45 nm CMOS process for supply voltages of 150 mV and 600 mV demonstrate that the proposed designs offer the best trade-off between delay, power, offset, and noise in ultra-low-voltage scenarios where railto-rail operation is not required.
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