Pipe-LPAQ: A Fully Pipelined Architecture for LPAQ Data
Pipe-LPAQ: A Fully Pipelined Architecture for LPAQ Data Compression on FPGA
Abstract:
LPAQ is a lossless data compression algorithm that uses adaptive weighting of context models to achieve a superior compression ratio, but it comes with high computational complexity. This complexity arises from the hash mapping and weight training computations in the context and mixer model update phases. These computations, which process data at the bit level, rely heavily on contextual histories, making it difficult to parallelize computations of multiple bits using simple parallel computing paradigms. Accordingly, scheduling a pipeline that support parallel processing for all LPAQ computing steps per bit is crucial to exploring the parallel potential and improving the compression speed of LPAQ. In this paper, we propose Pipe-LPAQ, a fully pipelined (non-blocking) architecture for accelerating the LPAQ compressor on FPGA. Pipe-LPAQ provides architectural support for the complex encoding com-putations of LPAQ with following distinctive modules: (1) A tailored hardware architecture for state computation, named GatherHash engine, which performs parallel hash operations for six context models while ensuring complex bit-level and byte-level data dependencies. (2) Four fully pipelined architectures for probability prediction computations, that implement parallel computations of StateMap, MATCH, MIX, and SSE components. When the pipeline is set up, Pipe-LPAQ can handle 1bit input data per cycle. Experimental results show that Pipe-LPAQ main-tains high compression ratios while achieving throughput ranging from 12.5 MB/s to 130.1 MB/s on a Xilinx Virtex UltraScale+ XCVU9P FPGA. This represents a 38× speedup compared to a high-performance CPU (Intel i9 13900K@5.8 GHz), and 23.4× and 1.91× speedups compared to state-of-the-art (SOTA) ASIC (TSMC 90nm CMOS@400 MHz) and FPGA (Xilinx XCVU9P@85 MHz) designs, respectively.
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Pipe-LPAQ: A Fully Pipelined Architecture for LPAQ Data Compression on FPGA
