A 48-Gb/s PAM-4 Transceiver With Transition Boosting and RLM Calibration for Next-Generation Memory Interface Testing
A 48-Gb/s PAM-4 Transceiver With Transition Boosting and RLM Calibration for Next-Generation Memory Interface Testing
Abstract:
As the demand for high-speed memory interfaces continues to grow, the need for effective testing methodolo-gies becomes increasingly critical. Traditional automatic test equipment (ATE) systems are limited in their capability to test advanced signaling methods such as pulse amplitude modulation-4 (PAM-4) due to their reliance on non-return-to-zero (NRZ) signaling. This article presents a PAM-4 transceiver designed to bridge the gap between the tester and the memory, boosting the PAM-4 testing data rate up to 48 Gb/s using existing NRZ-based ATE. The proposed work provides enhanced transition slope and ratio level mismatch (RLM) control through precise gate voltage adjustment, resulting in improved test accu-racy. The prototype was fabricated in 40-nm CMOS technology and occupies an active area of 2.34 mm2 . The proposed work operates at 48 Gb/s/pin, demonstrating an energy efficiency of 1.85 pJ/bit in write mode and 2.97 pJ/bit in read mode for the PAM-4 test, respectively.
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A 48-Gb/s PAM-4 Transceiver With Transition Boosting and RLM Calibration for Next-Generation Memory Interface Testing
