Proposed Abstract:

In modern cryptographic systems, the reliable generation of high-quality pseudo-random numbers is critical for ensuring data integrity and confidentiality, particularly in resource-constrained environments such as IoT devices, embedded systems, and sensor networks. While existing cryptographically secure pseudo-random number generators (CSPRNGs) based on algorithms like AES, DES, or SHA offer robust security, they often struggle with challenges like high resource demands, power consumption, and complexity, making them less suitable for low-power, compact applications.

This paper presents an innovative 32-bit CSPRNG architecture that combines the lightweight PRESENT block cipher with a dual polynomial-based pseudo-random number generator (PRNG) scheme. The proposed design incorporates two distinct polynomial PRNGs: one for generating the plaintext input and the other for producing the key input to the PRESENT cipher. This dual-PRNG strategy not only prevents repetitive random patterns but also significantly enhances the precision and randomness quality, bolstering resistance to cryptanalytic attacks.

The architecture is implemented in Verilog HDL and synthesized on the Xilinx Virtex-5 FPGA, a platform that strikes a balance between performance and efficiency. Comprehensive evaluations of the proposed system highlight key performance metrics such as area utilization, critical path delay, and power consumption. Results demonstrate that this approach achieves superior resource efficiency and reduced power consumption while maintaining or exceeding the security standards of more complex algorithms like AES and SHA.

Additionally, the theoretical foundations of dual polynomial PRNGs are explored, showcasing their ability to mitigate pattern repetition and enhance entropy and unpredictability. This feature is especially beneficial for applications requiring long-term operation without re-seeding, thereby extending the operational lifespan of secure systems in the field.

In summary, the proposed CSPRNG architecture represents a significant step forward in the design of secure and efficient random number generators, tailored for applications where both security and resource efficiency are critical. The integration of dual polynomial PRNGs with the PRESENT cipher establishes this work as a valuable contribution to cryptographic hardware design, with direct implications for advancing secure, low-power technologies such as IoT, RFID, and distributed network applications.

Software Implementation:

• Modelsim
• Xilinx

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Design and Implementation of 32-bit CSPRNG using the PRESENT cipher with Dual Polynomial PRNG for Enhanced Randomness and Precision