IEEE Transactions on VLSI 2024 Research Papers

( JANUARY 2024 ~TO~ JULY 2024)

PROJECT TITLE	TITLE FOR VLSI IEEE TRANSACTION
	LOW POWER
VLSI_2024_01_LP	Soft-Error-Aware SRAM With Multinode Upset Tolerance for Aerospace Applications
VLSI_2024_04_LP	An Isolated Frequency Compensation Technique for Ultra-Low-Power Low-Noise Two-Stage OTAs
VLSI_2024_11_LP	Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design
VLSI_2024_14_LP	A Wideband High-linearity Input Buffer Based on Cascade Complementary Source Follower
VLSI_2024_28_LP	An Ultra-Low Leakage and Wide-Range Voltage Level Shifter for Low-Power Digital CMOS VLSIs
VLSI_2024_31_LP	The High-Efficiency Optimization Design Method for Two-Stage Miller Compensated Operational Amplifier
	AREA EFFICIENT/ TIMING & DELAY REDUCTION
VLSI_2024_03_AE	Hardware-Efficient Logarithmic Floating-Point Multipliers for Error-Tolerant Applications
VLSI_2024_05_AE	A high-speed CRC-32 Implementation on FPGA
VLSI_2024_08_AE	In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays
VLSI_2024_12_AE	Design of a High-Performance Iterative Barrett Modular Multiplier for Crypto Systems
VLSI_2024_13_AE	A High-Performance Transparent Memory Data Encryption and Authentication Scheme Based on Ascon Cipher
VLSI_2024_22_AE	VLSI Architectures and Hardware Implementation of Ultra Low-Latency and Area-Efficient Pietra-Ricci Index Detector for Spectrum Sensing
VLSI_2024_23_AE	Flexible FPGA Gaussian Random Number Generators With Reconfigurable Variance
VLSI_2024_25_AE	A 32-Bit Ripple-Ling Hybrid Carry Adder
VLSI_2024_27_AE	A Reconfigurable Processing Element for Multiple-Precision Floating/Fixed-Point HPC
VLSI_2024_39_AE	A Novel Design of High Speed Multiplier Using Hybrid Adder Technique
VLSI_2024_40_AE	Efficient Pseudo Random Number Generator (PRNG) Design on FPGA
VLSI_2024_41_AE	Factored Systolic Arrays Based on Radix-8 Multiplication for Machine Learning Acceleration
VLSI_2024_46_AE	Algebraic Implementation of Extended Finite State Machine Networks
VLSI_2024_47_AE	Efficient Approximate Floating-Point Multiplier With Runtime Reconfigurable Frequency and Precision
VLSI_2024_49_AE	Accumulator-Based 16-Bit Processor for Wireless Sensor Nodes
	HIGH SPEED DATA TRANSMISSION
VLSI_2024_02_HS	Variable Conversion Approach for Design Optimization of Low-Voltage Low-Pass Filters
VLSI_2024_06_HS	A 35-Gb/s PAM-4 Transmitter With 7B4Q Full-Transition Avoidance and Area-Efficient Gm-Boosting Techniques
VLSI_2024_09_HS	Memory-Efficient Multiplier-Less 2-D DWT Design Using Combined Convolution and Lifting Schemes for Wireless Visual Sensors
VLSI_2024_10_HS	A Novel Design Approach and VLSI Architecture of Rationalized Bi-Orthogonal Wavelet Filter Banks
VLSI_2024_15_HS	On the Use of FIR Feedback in Bandpass Delta-Sigma Modulators
VLSI_2024_16_HS	Fast FPGA Prototyping to Explore and Compare New SPWM Strategies
VLSI_2024_17_HS	Kalman Filters Based Distributed Cyber-Attack Mitigation Layers for DC Microgrids
VLSI_2024_18_HS	A 0.14-nJ/b 200-Mb/s 2.7–3.5-GHz Quasi-Balanced FSK Transceiver With PLL-Based Modulation and Sideband Energy Detection
VLSI_2024_24_HS	Theory and Low-Power Design of Moving Accumulative Sign Filter
VLSI_2024_26_HS	Integrating OFDM Into Switching Power Supplies for Visible Light Communications
VLSI_2024_29_HS	A Low-Power and Low-Latency Speech Feature Extractor Based on Time-Domain Filter Bank
VLSI_2024_32_HS	A New Design of Low Hardware Cost and Low Power Programmable FIR Filters
VLSI_2024_33_HS	DFT-Based Method for Accurate I/Q Imbalance Estimation
VLSI_2024_37_HS	FPGA Implementation of Correlator for Direct Sequence Spread Spectrum (DSSS) Systems
VLSI_2024_42_HS	A Check-and-Balance Scheme in Multiphase Delay-Locked Loop
VLSI_2024_43_HS	Fractionally-Spaced Equalizers as Clock and Data Recovery Loops
VLSI_2024_44_HS	A 71.2-μW Speech Recognition Accelerator With Recurrent Spiking Neural Network
VLSI_2024_45_HS	A New ISA for High-Speed and Area-Efficient ALPG
	VLSI Design of Image, Video and Audio Processing
VLSI_2024_19_IM	HDSuper: High-Quality and High Computational Utilization Edge Super-Resolution Accelerator With Hardware-Algorithm Co-Design Techniques
VLSI_2024_20_IM	ESSR: An 8K@30FPS Super-Resolution Accelerator With Edge Selective Network
VLSI_2024_21_IM	ACE-CNN: Approximate Carry Disregard Multipliers for Energy-Efficient CNN-Based Image Classification
VLSI_2024_30_IM	Logarithmically Optimized Real-Time HDR Tone Mapping With Hardware Implementation
VLSI_2024_34_IM	A Low Cost FPGA Implementation of Retinex Based Low-Light Image Enhancement Algorithm
VLSI_2024_34_IM	A low complexity JPEG coding system
VLSI_2024_36_IM	A High-Speed Computational Pipeline Single MAC-Based VLSI Architecture for Real-Time Signal and Image Processing

Download VLSI IEEE PROJECTS 2024

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  • Timing & Delay Reduction 2024 VLSI Projects
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