Design methodology for ultrahigh-speed 5-2 and 7-2 compressors has been illustrated in this article. With the help of introduced procedure, the gate-level delay has been reduced considerably when compared with the previous designs, while the total transistor and gate count remain in a reasonable range. By starting the discussion for the carry rippling problem in n – 2 compressors, the method has been developed for 5-2 compressor and is expanded for 7-2 architecture, which shows 32% and 30% improvement in speed performance for these structures, respectively. Also, the careful design considerations have been taken into account to keep other characteristics, such as power and active, are at a reasonable level. Moreover, for a fair comparative conclusion, the best-reported circuits have been redesigned, and their parasitic elements were extracted utilizing the same technology employed for the synthesis of the proposed circuits. Finally, a typical 16 × 16 bit multiplier has been implemented to investigate the efficiency of the designed compressor blocks. Based on the postlayout simulation results provided using HSPICE for TSMC 0.18-μm standard CMOS technology and 1.8-V power supply, the proposed compressors demonstrate better speed performance and power-delay product (PDP) factor over previous works. As the results depict, the delay of 303 ps has been achieved for the 5-2 compressor while the measured delay of the designed 7-2 compressor is 464 ps.
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Very Fast, High-Performance 5-2 and 7-2 Compressors in CMOS Process for Rapid Parallel Accumulations
