TRIM: Acceleration of Multiplication-Less Neural Networks
TRIM: Acceleration of Multiplication-Less Neural Networks via Versatile Sparsities
Abstract:
Recently, multiplication-less neural networks (L1NNs), replacing multiplication-intensive dot products with addition-only `1 -distance kernels have emerged to enhance energy efficiency and speed with negligible degradation of accuracy. Despite these gains, such models suffer from pruning challenges that can negate their benefits. In this work, we identify the root cause of these challenges and introduce a novel method called synapse pruning, which is explicitly designed for L1NNs to overcome them for the first time. Building upon this algorithmic innovation, we present TRIM, an algorithm-hardware co-design framework that sparsifies and accelerates L1NNs to achieve ultra-high energy efficiency and speed. On the algorithmic side, we propose structured synapse pruning tailored for hardware-friendly N : M sparsity patterns for L1NNs. On the hardware side, we introduce a sparse processor architecture that efficiently exploits both the proposed N : M structured synapse sparsity and the intrinsic unstructured weight and activation sparsities in L1NNs by skipping redundant operations. Additionally, an N : M sparsity-aware elastic mapping technique is introduced to maximize hardware utilization and data reuse. Evaluations on seven benchmarks demonstrate that TRIM achieves up to 87.5% unstructured sparsity and up to 81.3% structured sparsity with less than 1% accuracy loss. Implemented in a 65 nm technology, our processor achieves 5.22 TOPS/W and 1.17 TOPS/mm2 , surpassing the existing SOTA L1NN accelerator by 1.7× in energy efficiency and 14.9× in area efficiency. The source code is available at: https://github.com/XZH28/TRIM-Sparse-L1-Distance-Net.git
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TRIM: Acceleration of Multiplication-Less Neural Networks via Versatile Sparsities
