Scalable Network-on-Chip Design for FPGA Implementation
Scalable Network-on-Chip Design for FPGA Implementation
Abstract:
Network-on-Chip (NoC) technology has become a fundamental solution to address communication bottlenecks and scalability challenges in modern System-on-Chip (SoC) architectures. This paper presents a fully automated and scalable NoC design framework capable of generating synthesizable Verilog code for diverse topologies, including Mesh, Torus, Butterfly Fat Tree (BFT), and Custom configurations. The framework, based on a wormhole router architecture, automatically configures interconnections, routing paths, and network parameters according to user specifications, eliminating manual intervention and reducing design time errors. The generated NoC architectures were synthesized and verified on a Xilinx Virtex-7 Field Programmable Gate Array (FPGA) using Vivado, demonstrating design adaptability and efficiency. Experimental results show up to ∼ 12, 500 speed-up for Mesh, ∼ 11, 500 for Torus, ∼ 10, 800 for BFT, and ∼ 10, 200 for Custom topologies compared with manual approaches. The proposed design was evaluated for throughput, latency, packet delivery ratio (PDR), and energy per packet. Results show that the BFT topology delivers the highest PDR (98.2%) and the lowest energy consumption (1.80 nJ), confirming the framework scalability. Overall, the AutoNoC framework offers a reconfigurable, topology-independent, and FPGA-compatible solution for scalable SoC communication.
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Scalable Network-on-Chip Design for FPGA Implementation
