Proposed Title :

FPGA Implementation of 16-Bit Variable Precision Floating Point Multiplier using XOR-MUX Modified Booth Encoding Method with Wallace Tree Adder

Improvement of this project :

• To design the 16-Bit Variable Precision Floating Point Multiplier using Area Delay Power Efficient XOR-MUX Full Adder instead of Conventional Full Adder.

• To design the Reduced Hardware Resources based on Booth Multiplier and Waller Tree Adders for Mantissa Multiplications.

Software Implementation:

• Modelsim
• Xilinx

Proposed System:

A variable-precision approximation floating-point multiplier is suggested for use in this short article with the purpose of making deep learning computations more energy efficient. The architecture that has been suggested offers support for approximation multiplication using the BFloat16 format. In deep learning models, the input and output activations often follow a normal distribution. This distribution is inspired by the posit format. For numbers with varying values, different precisions may be used to represent them. In the architecture that was presented, changing the amount of approximation is accomplished by the use of posit encoding, and the value of the product exponent is what determines the level of accuracy achieved by the calculation. In the case of a big exponent, the mantissa is subjected to a multiplication with a lower accuracy, but in the case of a small exponent, the calculation is subjected to a greater precision. The proposed design makes use of truncation as an approximation approach, with the number of bit locations that are going to be truncated being determined by the values of the product exponent. To reduce the logic size in the variable precision floating point multiplier, here proposed architecture present with area, delay and power efficient XOR-MUX Modified Booth Encoding Method with Wallace Tree Adder, in will reduce the number of logic gates in the precision floating multiplier. Finally, this work was developed in Verilog HDL, and synthesize on Xilinx Vertex-5 FPGA, and compared all the parameters in terms of area, delay and power.

” Thanks for Visit this project Pages – Buy It Soon “

Variable-Precision Approximate Floating-Point Multiplier for Efficient Deep Learning Computation