Software Implementation:
- Modelsim
- Xilinx
Objective of this project:
The primary objective of this project is to design, implement, and evaluate 16-bit, 32-bit, and 64-bit versions of the PRESENT cipher to explore its suitability for secure communication in resource-constrained environments, such as IoT devices, RFID tags, and sensor networks. This project aims to:
- Develop and Implement: Create Verilog HDL implementations of the PRESENT cipher with varying block sizes (16-bit, 32-bit, and 64-bit) and synthesize these designs on the Xilinx Virtex-5 FPGA platform.
- Optimize Performance: Analyze and optimize key performance metrics, including area (slice registers, LUTs, and occupied slices), delay, power consumption, and input/output block utilization, to ensure the cipher’s efficiency and effectiveness in constrained environments.
- Compare Configurations: Perform a comparative analysis of the different implementations to understand the trade-offs between security, resource utilization, and performance, particularly focusing on the impact of block size and number of rounds.
- Assess Applicability: Evaluate the practical applications of the PRESENT cipher in real-world scenarios, such as secure data transmission, device authentication, and lightweight encryption, identifying the most suitable configuration for various use cases.
- Enhance Security Awareness: Highlight the balance between security and efficiency in the context of lightweight cryptographic solutions, providing insights into the limitations and strengths of the PRESENT cipher for low-power, low-resource devices.
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Ultra Lightweight Cryptography: Exploring the Application and Optimization of the PRESENT Cipher in Constrained Devices
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