Proposed Title:

Design and Comparisons of Soft Error Aware 16T SRAM Arrays using 45nm and 65nm CMOS Technology for Aerospace Applications

Improvement of this project :

• To developed single bit 16T SRAM design using 45nm and 65nm CMOS Technology.

• To developed 8×8 array SRAM architecture which using 45nm and 65nm CMOS Technology and compare the parameters in terms of area, delay and power.

Software Implementation:

• Tanner EDA

Proposed System:

In this research, we present the design and comparative analysis of soft-error-aware 16T SRAM arrays using 45nm and 65nm CMOS technologies, with a focus on aerospace applications. Aerospace environments are highly susceptible to radiation-induced soft errors, demanding the development of robust memory systems. We begin by designing a single-bit 16T SRAM cell optimized for multinode upset tolerance, incorporating advanced error correction and radiation-hardening techniques to enhance reliability. The single-bit cell design is then scaled to an 8×8 SRAM array architecture. Both the 45nm and 65nm versions of the array are developed and simulated to evaluate key performance metrics, including area, delay, and power consumption. The results indicate that while 45nm technology achieves better performance and area efficiency, 65nm technology excels in power savings and reliability. This comprehensive study underscores the importance of technology selection in optimizing SRAM design for high-reliability aerospace applications, offering a framework for future advancements in radiation-hardened memory systems.

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Soft-Error-Aware SRAM with Multinode Upset Tolerance for Aerospace Applications