Proposed Title :

• FPGA based Low Power Resource Efficient Multi Ported SRAM based Ternary Content Addressable Memory (REST)

Improvement of this Project:

• To Modified the Single port memory architecture to Multi ported memory, and also increases the memory size of 512 x 72 bit, via the implementation on VHDL, with synthesized in Xilinx Kintex-7 FPGA, and shown the comparison of area, power and delay

Software implementation:

• Modelsim
• Xilinx 14.2

Proposed System:

The implementation of Proposed system of SRAM-based TCAM is to search contents stored in the memory. This is done by accessing stored data by content rather than by address; this is unlike static random access memory(SRAM), which accesses content using the address, here we are modified the SRAM of single ported to Multi ported, so it will search the contents stored in the memory using multi port. The utilization of block or Distributed RAM is critical performance factor for multi-ported memory design on field programmable gate array (FPGA), this paper introduced a new perspective and more efficient way of using a conventional memory of Multi input and Multi output port based upon TCAN memory size.

Field Programmable gate array,  have been broadly used in fast prototyping of complex digital systems. FPGA contain programmable logic, arrays, usually referred to a slices. Slices can be configured in to different logic functions. The flexible routing channel can support data transferring between logic slices. In addition to implementing logic operations, if needed the slices can also be used as storage elements, such as flip flops, registers, or other memory modules. In this same way via the TCAM signal ported memory will be modified to Multi ported memory, with reduced the slice configuration in FPGA. The modified architecture of Resource efficient multi ported SRAM based TCAM is shown in below architecture.

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Resource Efficient SRAM based Ternary Content Addressable Memory

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