Proposed Title :

FPGA Implementation of Low Power Split Radix FFT Processors Using 2048 Point Radix-4 Butterfly Units

Improvement of this project :

• Increased the Size of Radix-2 to Radix-4, and Increases the Point 1024 to 2048, with complex valued transform, and show the performance of area, power and delay.

Software implementation:

• Modelsim
• Xilinx

Proposed System:

In this paper, we are proposed to Increases the size of radix-2 to radix-4, and increases the point 1024 to 2048, with complex valued transform, and show the performance of area, power and delay. With Radix-4 Burst I/O Solution, the FFT uses Radix-4 Butterfly processing engine. It loads and/or unloads data separately from calculating the transform. Data I/O and processing are not simultaneous. When the FFT is started, the data is loaded. After a full frame has been loaded, the core computes the transform. When the computation has finished, the data can be unloaded, but cannot be loaded or unloaded during the calculation process. The data loading and unloading processes can be overlapped if the data is unloaded in digit reversed order. This architecture has lower resource usage than the Pipelined, Streaming I/O architecture, but a longer transform time, and supports point sizes from 64 to 65536. Data and phase factors can be stored in block RAM or in distributed RAM (the latter for point sizes less than or equal to 1024).

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Low Power Split Radix FFT Processors Using Radix 2 Butterfly Units