Proposed Title:

FPGA Implementation of 8^th Order ECG Filter design with Optimizing Performance Truncated Multipliers

Improvement of this project :

• To design 8^th Order FIR Filter and IIR Filter design for ECG applications.

• To design FIR Filter which using Window mode, Rectangular form.

• To design IIR Filter which using Chebyshev Type 2, Direct Form II design architecture.

• Both the Filter design compared with Conventional and Truncated multiplier and proved the performance analysis of Area, Delay and power.

Software Implementation:

• Modelsim
• Xilinx ISE

Proposed System:

The goal of this research is to design and implement digital filters—Finite Impulse Response (FIR) and Infinite Impulse Response (IIR)—based on Field Programmable Gate Arrays (FPGA) using the Xilinx ISE Design Suite. Low-pass digital filters are implemented for various medical applications to enable faster detection and prediction of issues. Specifically, ECG signals are processed in real-time to provide accurate heart rate predictions. Therefore, these ECG filters require high efficiency, minimal logic size, and low power consumption. This study presents a comparison and analysis of FIR and IIR filters. To reduce logic size, a truncated multiplier is applied and its performance is evaluated against conventional methods. For signal accuracy, the FIR filter is designed using the Rectangular-Window method, and the IIR filter is designed using the Direct Form II Chebyshev Type II method, both utilizing an 8th order design. The implementation is carried out using the Xilinx ISE Design Suite. The performance is measured by the difference in the ECG signal in simulation. Using FPGA with digital filters in this research offers significant advantages.

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High Performance FIR and IIR Filters Based on FPGA for 16 Hz Signal Processing