Improvement of this Project:

•  we propose a partially parallel structure to encode long polar codes efficiently. To clearly show the proposed approach and how to transform the architecture, a 4-parallel encoding architecture for the 16-bit polar code is exemplified in depth. The fully parallel encoding architecture is first transformed to a folded from and then the lifetime analysis and register allocation are applied to the folded architecture. Lastly, the proposed parallel architecture true for long polar code is described.

Software implementation:

• Modelsim
• Xilinx 14.2

” Thanks for Visit this project Pages – Buy It Soon “

FPGA Implementation of Partially Parallel Encoder Architecture for Long Polar Code