Proposed Title:

Design and Implementation of Logarithmic Floating Point Multiplier using Brent Kung Adder for FPGA Based Error Tolerant Applications

Improvement of this project :

• To develop design and implement logarithmic Floating point multiplier using approximate computing technique and simple operators like adders, and multiplexers, here not used any internal multipliers.

• To replace the conventional adders with the Brent Kung Parallel Prefix adder within the single precision multiplier design to enhance efficiency, further reducing area, and power usage while maintaining computational accuracy.

• To design this architecture in Verilog HDL, and synthesize using Xilinx Zynq FPGA, and compared all the parameters in terms of area, delay and power.

Software Implementation:

• Modelsim
• Xilinx Vivado

Proposed System:

In this project, we develop and implement a novel logarithmic floating-point multiplier tailored for error-tolerant applications. Leveraging approximate computing techniques, the proposed design utilizes simple operators such as adders and multiplexers, entirely avoiding internal multipliers to enhance hardware efficiency. A significant innovation in our approach is the integration of the Brent-Kung parallel prefix adder, replacing conventional adders to further reduce area and power consumption while maintaining computational accuracy. The architecture is meticulously designed in Verilog HDL and synthesized using the Xilinx Zynq FPGA platform. Comprehensive evaluations are conducted to compare the proposed multiplier against traditional designs, focusing on key metrics such as area, delay, and power. The results demonstrate significant improvements, making our design an optimal choice for resource-constrained, computation-intensive applications such as JPEG image compression and neural network training.

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Hardware-Efficient Logarithmic Floating-Point Multipliers for Error-Tolerant Applications