Proposed Title:

FPGA Implementation of CRC-Enhanced BCH and Hamming Code for Fault Tolerant Parallel Filter Architecture in GPS and Space Applications

Proposed Abstract:

This project introduces a novel fault-tolerant parallel filter architecture that integrates Cyclic Redundancy Check (CRC) with BCH and Hamming Error Correction Codes (ECC) to improve fault detection and correction in GPS and space applications. By embedding CRC within both the encoder and decoder, this design enhances traditional error correction mechanisms, allowing for more efficient handling of robust error detection, particularly for burst errors and complex error pattern commonly found in space environments. The CRC-enhanced architecture ensures higher reliability and data integrity, addressing the limitation of traditional error correction methods. The CRC-BCH combination addresses multiple-bit errors, while the CRC-Hamming combination corrects single-bit errors, ensuring higher data integrity under harsh environmental conditions. By embedding CRC within both the encoder and decoder, the architecture provides a lightweight, power-efficient solution, reducing the risk of undetected errors, especially when the primary ECC reaches its correction limit. A Fault Injector simulator is employed to test the robustness of the design by introducing random faults. The architecture is implemented in Verilog HDL and synthesized on a Artix-7 FPGA, with key performance metrics like area, power, delay, and error correction efficiency evaluated for space communication and data processing systems.

Software Implementation:

• Modelsim
• Xilinx

” Thanks for Visit this project Pages – Buy It Soon “

Efficient CRC-BCH Unified Encoder for Global Positioning System