Proposed Title:

FPGA Implementation of Efficient Approximate Floating Point Multiplier using Brent Kung Adder for Optimized Area and Power Efficiency

Proposed Abstract:

The growing demand for energy-efficient Deep Neural Networks (DNNs) has highlighted the need for hardware solutions that can balance computational precision with reduced area and power consumption. This project presents the design of an efficient approximate floating-point multiplier incorporating the Brent-Kung Adder, which optimizes area and power efficiency. The proposed design features runtime reconfigurable precision and clock frequency, enabling dynamic trade-offs between computational accuracy and energy savings. Developed in Verilog HDL and synthesized using Xilinx Vivado, the design is evaluated for various parameters, including area utilization and power consumption. Experimental results demonstrate significant reductions in both area and power, while maintaining acceptable accuracy levels for DNN inference tasks, making it ideal for resource-constrained edge devices. This work highlights the advantages of combining approximate computing with optimized adders for energy-efficient hardware acceleration.

Software Implementation:

• Modelsim
• Xilinx

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Efficient Approximate Floating-Point Multiplier with Runtime Reconfigurable Frequency and Precision